Design and Analysis of FinFET models based Ternary Half Subtractor
2024 3rd International Conference for Innovation in Technology (INOCON)(2024)
摘要
The introduction of multivalue logics in the field of digital electronics has been recognized as a significant achievement, offering resolutions to the constraints imposed by binary logic. Within the field of multivalue logic, ternary logic is generally considered an innovative method. This article presents a comprehensive overview of the design of a ternary half subtractor using 18nm FinFET technology, implemented via the use of the Virtuoso tool offered by Cadence. The evaluation of the Subtractor's performance is carried out by a comparison of the results obtained using SVT and HVT FinFET models. The obtained simulation results reveal power consumption values of 33.70 and 27.76μW, transient delay values of 10.31 and 10.36ns, and power delay product values of 347.44 and 287.59 (x 10-15 J) for the SVT and HVT FinFET models, respectively. The proposed design of a ternary half subtractor has potential for energy efficiency in the context of data compression and error detection applications.
更多查看译文
关键词
FinFET technology,Ternary logic,Ternary Half Subtractor
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要