2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs.

The gate driver design for power semiconductor devices affects overall efficiency and performance. This research presented an AGD (active gate driver) that detects the Miller plateau during the driving signal's turn-on and turn-off using a 2-level Miller detector. It has a power gating mechanism that reduces the power consumption of the AGD. Furthermore, the Equalizer in the AGD ensures that all MOS devices in the buffer arrays are utilized. The AGD design has been implemented in TSMC $\mathbf{0}.\mathbf{18}-\mu \mathbf{m}$ HV CMOS $(\mathbf{T}\mathbf{18}\mathbf{HVG}\mathbf{2})$ process. The functionality of the AGD design was verified by the all-PVT-corner post-layout simulations with $\mathbf{C}_{load}=\mathbf{2}\ \mathbf{nF}$ and an operating frequency of 500 kHz. It has an average combined static and dynamic power dissipation of 288.8 mW. Finally, the power gating mechanism provides a 65.9 mW static power reduction based on two cycles comparison (with and without power gating).