Universal Dielectric Breakdown Modeling under Off-State TDDB for Ultra-Scaled Device from 130nm to 28nm Nodes and Beyond
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY（2024）
Key words
Logic gates,Electric breakdown,Stress,Leakage currents,Dielectrics,Silicon,Impact ionization,BTBT,CMOS,DAHC,leakage,off-state damage,soft and hard breakdown,SILC,sub-threshold current,TDDB
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