Complementary Negative Capacitance Field-Effect Transistors Based on Vertically Stacked Van Der Waals Heterostructures

Complementary field-effect transistors (CFETs) with a vertically stacked n-FET/p-FET configuration can provide a promising solution to boost area efficiency. However, the substantial power dissipation exhibited by these CFET devices poses a notable challenge to the energy efficiency. By combining a negative-capacitance field-effect transistor (NCFET) and a CFET, the problem of excessive power consumption can be solved. By using a negative-capacitance gate stack, the supply voltage (V-dd) applied to the gate of the CFET is increased, resulting in a reduction in power consumption. Here, we experimentally demonstrate a vertically integrated complementary negative capacitance field-effect transistor (NC-CFET) that combines tungsten diselenide (WSe2) p-NCFET and molybdenum disulfide (MoS2) n-NCFET. With the hexagonal boron nitride/copper indium thiophosphate CuInP2S6 (CIPS) dielectric stack, both n-type and p-type van der Waals (vdW) NCFETs exhibit sub-60 mV/decade switching characteristics. The vdW NC-CFET exhibits a voltage gain of 78.34 and a power consumption of 129.7 pW at a supply voltage of 1 V. These device characteristics demonstrate the great potential of the vdW NC-CFET for high density and low power applications.