On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules.

Although built-in self-repair (BISR) techniques have been widely used to improve memory yield, their applications to the testing of 3D systems-on-chip (SoC) remained primarily unexplored. In this manuscript, we present a multi-stage approach to implement BISR in 3D SoCs with an aim to (i) reduce test time by proposing a test scheduling technique satisfying given power constraints, (ii) reduce the number of BISR modules, and (iii) to place BISR circuitry in suitable layers for facilitating thermal dissipation. Experimental results on several SoC benchmarks show that our approach reduces both test time as well as the cost of BISR architecture in most cases.