A 6-Ghz 78-Fs $_{\mathrm{rms}}$ Double-Sampling PLL with Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving $-$ 92-Dbc Reference Spur and $-$ 258-Db FOM
IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS（2024）
Key words
Phase locked loops,Voltage-controlled oscillators,Jitter,Clocks,Wireless communication,Transistors,Prototypes,Double sampling (DS),figure of merit (FOM),frequency synthesizer,low jitter,low power,low spur,phase detector (PD),phase-locked loop (PLL),phase noise (PN),reference sampling (RS),subsampling (SS),type-I
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