A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering
2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)(2024)
摘要
To alleviate the performance and energy overheads of contemporary
applications with large data footprints, we propose the Two Level Perceptron
(TLP) predictor, a neural mechanism that effectively combines predicting
whether an access will be off-chip with adaptive prefetch filtering at the
first-level data cache (L1D). TLP is composed of two connected
microarchitectural perceptron predictors, named First Level Predictor (FLP) and
Second Level Predictor (SLP). FLP performs accurate off-chip prediction by
using several program features based on virtual addresses and a novel selective
delay component. The novelty of SLP relies on leveraging off-chip prediction to
drive L1D prefetch filtering by using physical addresses and the FLP prediction
as features. TLP constitutes the first hardware proposal targeting both
off-chip prediction and prefetch filtering using a multi-level perceptron
hardware approach. TLP only requires 7KB of storage. To demonstrate the
benefits of TLP we compare its performance with state-of-the-art approaches
using off-chip prediction and prefetch filtering on a wide range of single-core
and multi-core workloads. Our experiments show that TLP reduces the average
DRAM transactions by 30.7
state-of-the-art cache prefetchers but no off-chip prediction mechanism, across
the single-core and multi-core workloads, respectively, while recent work
significantly increases DRAM transactions. As a result, TLP achieves geometric
mean performance speedups of 6.2
workloads, respectively. In addition, our evaluation demonstrates that TLP is
effective independently of the L1D prefetching logic.
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关键词
Hardware Prefetching,Off-Chip Prediction,Prefetch Filtering,micro-architecture,Graph-Processing
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