On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm

The field of digital signal processing has been receiving increasing attention over the years because of its widespread applications in various fields of science, engineering and technology. In connection to this, design of finite impulse response (FIR) filter has drawn enough attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this work, one novel Right to Left (R2L) algorithm is proposed which can minimize the number of multiplier-adders for the powers-of-two FIR filter. The requirement of such adders essentially depends upon the number of such non-zero entries and the word-length of the input signal. Comparative study has been performed amongst few such hardware efficient realizations of digital filters. Finally, the proposed approach has been implemented using Xilinx Plan Ahead 14.7 so as to have a clear understanding about the requirement of different hardware blocks on a field programmable device.