On the Feasibility of using FPGA's for Efficient Topology Optimization

Topology Optimization is a class of structural optimization problems, where the classical goal is to find the best layout of a structure ensuring that it can withstand a set of prescribed forces, while being as light as possible. Since this class of optimization problems are computationally expensive, a vast amount of research is directed at how to increase the speed at which these problems can be solved. Previous work on accelerating topology optimization problems includes designing more efficient algorithmic approaches and better utilizing hardware resources. However, to the best of our knowledge, no previous attempts have been made to accelerate topology optimization using a hardware accelerator implemented on an FPGA. This paper presents a hardware accelerator for topology optimization, designed to solve compliance minimization problems in three dimensions. The accelerator is implemented as an application-specific instruction set processor, using a custom instruction set architecture designed specifically for the minimum compliance problem. The developed accelerator is able to solve problems 4.8-8.2 times faster than a modern computer, while operating at a fraction of the clock frequency. Although the current accelerator has only been proven to work on coarse meshes, it is reasonable to assume that the speedup will also carry over to larger optimization problems. This indicates that FPGA-based acceleration of topology optimization problems is viable.