A 16B 5MS/s Pipeline-SAR ADC in 180nm CMOS

This paper presents the design and simulation of a 16-bit pipeline-SAR Analog-to-Digital Converter (ADC) using a "6+10" architecture. The design aims to alleviate residue amplifier pressure by employing dynamic and static amplifiers in the first and second stages, respectively. The residue amplifier design incorporates folding interpolation and auxiliary amplifier sharing to enhance gain accuracy. Auto-zeroing mitigates flicker noise influence. The design employs the SMIC 180nm CMOS process. At 250 kS/s, the circuit achieves 16.1-bit ENOB and 98 dB SNR. At 1 MS/s, it attains 16.5-bit ENOB and 101 dB SNR. Results showcase robust performance and confirm efficacy for high-precision analog-to-digital conversion. Power consumption is 55 mW in simulation.