Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration.

In this paper, we propose a timing-driven tier partitioning approach to achieve better timing closure for 3D ICs. Precisely, we collect the potential candidates of timing critical paths from the pseudo-3D placement result and apply the timing information into the existing tier partitioning algorithm, the purpose of which is to induce the existing tier partitioning algorithm to assign the cells in a same timing critical path to a similar tier. Our experiments with open-source benchmark circuits confirm that the proposed timing-aware tier partitioning method achieves 18.98% improvement compared to the original bin-based FM min-cut algorithm, without any design quality degradation.