10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.

Fractional-N PLLs are plagued by spurs that result from interaction between the shaped quantization noise introduced by the controller of the feedback divider and non-linearities in the loop. In addition to fixed spurs associated with the fractional input to the divider controller, fractional-N PLLs can also exhibit (i) fixed spurs, whose positions depend on the initial phase setting, and (ii) moving or “wandering” spurs. These become important in applications such as phased arrays that require phase offsets between multiple PLLs and radar applications where wandering spurs can be wrongly interpreted as targets. The divider controller in a fractional-N PLL is commonly implemented as a digital delta-sigma modulator (DΔΣM). The principal source of non-linearity is a time-interval measurement subsystem (TIMS), whose output is a measure of the time interval between the edges of the reference and feedback-divider signals. In a charge-pump (CP) PLL (CP-PLL), the TIMS comprises a phase frequency detector (PFD) and a CP and is typically characterized by a smooth non-linearity. In an all-digital PLL (ADPLL), the TIMS is usually a time-to-digital converter (TDC) that introduces a quantization non-linearity. In bangbang (BB) BB PLLs, the ref and div edges are usually brought into closer alignment using a multibit digital-to-time converter (DTC) before measuring the difference between them. The DTC introduces an additional quantization mismatch and other non-linearities.