Monolithic 3-D Integration of Counteractive Coupling IGZO/CNT Hybrid 2T0C DRAM and Analog RRAM-Based Computing-In-Memory

Computing-in-memory (CIM) based on analog resistive random access memory (RRAM) emerges as an energy-efficient technology for edge artificial intelligence (AI), where a large amount of ON-chip data buffer is needed to implement complex neural networks. In this work, we report a novel InGaZnO $_{\textit{x}}$ (IGZO)/carbon nanotube (CNT) hybrid-polarity 2T0C DRAM as a backend-of-the-line (BEOL) compatible buffer, which is a monolithic 3-D (M3D) integrated with HfO $_{\text{2}}$ -based analog RRAM array and Si CMOS logic to demonstrate a M3D-BRIC chip. The structural integrity and proper function of each layer are systematically verified. In particular, by incorporating n-type ultralow leakage IGZO field-effect transistor (FET) for write transistor and p-type high-current CNT-FET for read, this unique hybrid-polarity 2T0C design achieves a decent retention and desirably large read currents. It also helps enhance the effective sensing window and, more importantly, resolve the charge injection issue via counteractive coupling. To demonstrate the computational advantage of M3D-BRIC architecture, a typical high-resolution (Hi-Res) video processing task is further implemented using the YOLOv3 network for object detection. The benchmark shows that the M3D-BRIC chip with BEOL 2T0C DRAM could achieve a 48.25 $\times$ higher processing capability compared to its 2-D counterpart.