16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking.

Hardware root of trust has become widely used in the industry with some companies mandating Trusted Platform Module (TPM) 2.0. One of the main components of TPM is the key-generation block. Physically unclonable functions (PUFs) generate unique IDs for each chip without any physical manipulation and hence undetectable by optical probing. Deep sub-micron process technology with significant process variation is well suited for constructing silicon PUFs which utilize the variation between transistors to generate the unique ID. However, one of the problems associated with the PUF array is that the readouts depend on the prevailing conditions, such as temperature, supply voltage and aging which may result in wrong key readout and failed authentication. The PUF undergoes an enrollment phase where helper data which is stored in fuses on chip is generated to assist the error control coding (ECC) block in correcting a certain percentage of errors in the PUF output, as shown in the Fig. 16.4.1. The helper data is used during the reconstruction phase to recover the correct key from potentially incorrect PUF data. The complexity of the ECC block and the size of the helper data increase nonlinearly with the increase in errors in PUF data. To simplify the ECC mechanism, we introduce an error detection and hard masking step, identifying PUF cells prone to generating erroneous outputs. These marked cells are then treated as invalid and excluded from the key generation process as shown in Fig. 16.4.1. The fundamental concept behind unstable cell detection involves introducing a small bias to alter the characteristic of a specific stage within a PUF cell to identify potentially unstable cells. The cells with a difference in output with and without bias injection are the ones which are susceptible to change when operating conditions change. Unstable cell detection has been demonstrated in [3–6] where either supply, body bias, or capacitance modification is utilized for bias injection. However, these mechanisms are not very convenient in deep sub-micron processes with multiple layout related effects and stringent DRC and DFM rules.