7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS

2024 IEEE International Solid-State Circuits Conference (ISSCC)(2024)

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摘要
The growing demand for cloud computing and artificial intelligence applications pushes wireline transceivers to higher data rates. DSP-based transmitters (TX) and receivers (RX) have achieved 224Gb/s [1–2], but unfortunately consume substantial power. Furthermore, 224Gb/s SerDes places more stringent demands on the signal integrity of the passive components, such as connectors, channels, and packages. In contrast, the single-ended scheme may be a practical and cost-effective solution for 224Gb/s data rates. First, it doubles the throughput density by delivering two single-ended signals over one differential channel. Furthermore, this scheme relaxes the Nyquist bandwidth for the passive components. Unfortunately, single-ended links exhibit severe crosstalk, particularly for long-channel scenarios. Previous crosstalk-cancellation (XTC) work [3] cancels the far-end crosstalk (FEXT), but at low data rates. The recent single-ended links achieve 40Gb/s/pin [4], FEXT is minimal but transmission is limited to short distances $(\lt100$ mm). This paper presents a $2 \times 112$ Gb/s PAM-4 single-ended reconfigurable XTC transceiver (TRX) employing a mismatch-mitigation single-ended-to-differential (S2D) converter and a 4-tap RX FFE in 28nm CMOS, compensating for up to 31dB loss at a power efficiency of 2.77pJ/b.
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关键词
28-nm CMOS,Data Rate,Low-pass,Current Source,Bit Error Rate,Ethernet,Passive Components,Demand For Applications,Hold Time,Datapath,Timing Diagram,Low Data Rate,Clock Generator,Stringent Demands,Power Breakdown
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