Enhanced gate biasing resilience in asymmetric and double trench SiC MOSFETs towards generalized highly reliable power electronics

The gate oxide quality in SiC MOSFETs presents a significant challenge, particularly at temperatures exceeding 175 C. This predicament arises from the gate oxide interface's propensity to trap or release charge carriers, compromising device ruggedness. In mainstream SiC MOSFETs, the gate oxide in the trench corner confronts the demanding task of enduring higher electric field strengths, thereby posing a substantial risk to overall device reliability. As a result, research entities are proactively involved in improving the SiC/oxide interfaces to enhance the devices' resilience against elevated E-field. This endeavor aims to maintain the favorable characteristics of the trench SiC MOSFETs, including low on-state resistance, minimal parasitic capacitance, and exceptional switching performance. Thus, the implementation of a streamlined process becomes crucial to fortify the trench corner, ultimately yielding boosted E -field immunity. In this report, our research focuses on enhancing the reliability of trench corner in SiC MOSFET devices. Specifically, we employ spacer etch technology to selectively shield the trench corner with high-K heterolayers, thereby enhancing the device's ability to withstand higher Efield strengths (59.2 % reinforcement) while mitigating the risk of hidden defects. Importantly, compared to the structure without protection, at high-K shielded layer contact angles ranging from 90 to 150 degrees, the E -field decreases, correlated the enhanced reinforcement at larger angles. Furthermore, such technology enables higher Efields and greater circuit capacity at the bottom of trench gate, leading to enhanced device reliability. Our studies confirm that the developed device structure exhibits simplicity, reliability, maturity, and controllability, rendering it suitable for large-scale integration applications.