The Study and Modeling of saturation drain voltage for junctionless FinFET

In this work, the mechanism and model of saturation drain voltage (Vds,sat) for Junctionless FinFET (JLF) are investigated. The Vds,sat of JLF is observed to increase linearly with gate voltage in all operation regions. A physics-based Vds,sat calculation model of JLF is built for fast and simple extraction of saturation drain voltage. The effects on Vds,sat of device parameters such as gate length, Fin height, Fin width and doping concentration, as well as device structure such as top gate and corner of the Fin, are discussed by simulation and model calculation. The results of model meet well with the simulation, and JLF has a low Vds,sat compared with other FinFETs. It shows that JLFs have potential prospect for lower power application in the future.