LPCHISEL: Automatic power intent generation for a chisel-based ASIC design

Chisel -based design description brings the objected -oriented as well as functional programming aspects inherent to software design into the digital design realm. The associated productivity benefits can especially be utilized to write deep learning (DL) accelerator generators using Chisel to cater to the diverse and swiftly evolving user requirements. Additionally such applicationspecific integrated circuits (ASIC) based edge accelerators particularly ought to be power efficient but the power intent description for these accelerators usually requires several low level design details that can adversely impact the productivity benefits accorded by their Chisel description. This work hence, presents an automated ASIC power intent description methodology based on chisel frontend i.e. LPCHISEL wherein, the modular naming/hierarchy and signal naming conservation of the Chisel-to-RTL flow is utilized to reduce the power intent description effort. The proposed methodology is validated and assessed by using Chisel descriptions of designs ranging from simple hierarchical ripple carry adder to more complex implementations of systolic array based ML accelerators. Via comparative analysis with state-ofthe-art approaches, we demonstrate considerable improvement in the design effort in addition to superior error performance in describing power intent of designs with both varying complexities and customization in the underlying power intent description process.