FPGA-based hardware implementation of chaotic opposition-based arithmetic optimization algorithm

The hardware implementation of optimization algorithms has gained significant attention due to its potential for augmenting performance and efficiency. This paper presents the hardware implementation of a Chaotic Opposition-Based Arithmetic Optimization Algorithm (COAOA). COAOA is inspired by integrating chaotic dynamics and opposition-based learning (OBL) principles in the original AOA algorithm. Inspired by chaotic maps, COAOA amplifies exploration and exploitation capabilities, while OBL enhances the search process by considering both positive and negative solution counterparts. Our proposed hardware implementation of COAOA harnesses Field-Programmable Gate Arrays (FPGAs) to accelerate optimization processes. Leveraging FPGA's parallel processing capabilities, the COAOA algorithm is efficiently parallelized and mapped onto the hardware architecture, streamlining arithmetic operations and governing algorithmic execution flow. To assess its efficacy, a comparison was made between the performance of the suggested structure and five alternative algorithms: opposition-based learning AOA (OAOA), Chaotic AOA, the original AOA, PSO and GA. Statistical analyses and tests were performed using benchmark functions like Rosenbrock, Rastrigin, Six-Hump CamelBack, and Zirilli functions. The empirical findings indicate the substantial acceleration achieved through the hardware implementation of COAOA compared to the original AOA algorithm and its variants. This compelling outcome positions COAOA as a viable solution for real-time optimization challenges, signifying its potential to significantly expedite optimization tasks in practical applications.