Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications

Approximate computing is a technique to obtain notable improvement in power and power-delay product parameters where accurate computation is not necessary. This paper presents a simple and energy-efficient approximate 1-blt ternary multiplier and approximate ternary half adder, which are used to implement $6\times 6$ approximate ternary multipliers. The $6\times 6$ ternary multipliers are implemented by introducing errors in generation or reduction stages. The proposed approximate ternary $6\times 6$ multipliers show good accuracy-power trade-off compared to existing designs; it exhibits an improvement up to 99.6% in terms of NMED*Power parameter compared to existing approximate multiplier designs. Further proposed ternary multipliers are evaluated using image processing applications.