Design of 1-1-1 Cascaded Discrete-Time Delta-Sigma Modulator based on Tracking Quantizer

In this article, a multi-bit discrete-time delta-sigma modulator based on tracking quantizer for use in telecommunication applications is presented. The proposed 4-bit quantizer uses a comparator, an internal digital-to-analog converter (DAC) and a digital control circuit to predict the integrator output within one clock pulse. In addition, the use of one comparator in the proposed quantizer reduces the power and area consumption of the proposed modulator. In order to study the performance of the proposed method, a 1-1-1 cascaded multi-bit discrete-time delta-sigma with 4-bit proposed quantizer is designed and simulated at the transistor level in 180 nm CMOS technology. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 73.2 dB in a bandwidth of 500 kHz. The oversampling ratio (OSR), power supply voltage, power consumption, Walden's figure of merit (FoMw) and Schreier's figure of merit (FoMs) of the proposed modulator are 32, 1.8 V and 3.3 mW, 0.91 pJ/conv-step and 154.30 dB, respectively.