A new model for parametrically evaluating the routability of GRM FPGA

We propose a new model for parametrically evaluating the routability of GRM FPGA. By studying GRM FPGA, we can evaluate two-level mux structure. The input of our model is architecture parameters, and output is the routability estimation. Our model first generates directed graphs, which are used to model the FPGA routing architecture, and then analyzes the directed graphs to obtain the routability estimate. We show that our model can correctly predict the trend of routability while costing less time.