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Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors

S. M Kifayat Kabir, Raihan Motalib, Fakrul Islam Javed,Chamak Ganguly, Saeed Hossen Rakib,Satyendra N. Biswas

2023 6th International Conference on Electrical Information and Communication Technology (EICT)(2023)

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Key words
Built in Self-Test (BIST),Memory,Fault Detection,Complexity Reduction,Test Pattern Generator (TPG)
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