30 Mb/mm2/layer 3D eDRAM Computing-in-Memory with Embedded BEOL Peripherals and Local Layer-wise Calibration based on First-Demonstrated Vertically-stacked CAA-IGZO 4F2 2T0C Cell

2023 International Electron Devices Meeting (IEDM)(2023)

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摘要
This paper, for the first time, reports fabricated and measured 2-layer vertically-stacked channel-all-around (CAA)-IGZO 4F 2 2T0C cells. Based on this area-efficient cell structure, an ultra-dense and robust 3D eDRAM computing-in-memory (CiM) accelerator with the local-computing scheme, consisting of stacked BEOL memory arrays, BEOL multiplexing peripherals, and FEOL local layer-wise calibration, is proposed. The highlights include: 1) first fabrication and measurement of vertically-stacked CAA-IGZO 2T0C cells, with record scaled cell size as low as 0.023 μm 2 , and long retention time up to 20s; 2) the 3D eDRAM CiM with embedded BEOL peripherals that realizes 1.54× higher maximum computing density than the counterpart with peripherals implemented in FEOL; 3) integrated LCU with data recovery function and readout calibration that reduces the impact of both inter-layer and intra-layer variations, achieving high accuracy up to 90% even with 20% relative variations and 8-layer stacking with 0.9× layer-wise performance decay. The measurement and evaluation results show that the proposed 3D eDRAM CiM achieves ultra-high memory and computing density up to 30 Mb/mm 2 /layer and 50 TOPS/mm 2 .
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关键词
Local Calibration,Data Recovery,Performance Decay,Electrode,Vertical Line,Memory Cells,Density Data,Lookup Table,Stacked Layers,Circuit Design,Atomic Layer Deposition,Parasitic Capacitance,Metal-insulator-metal,Dry Etching,Multilayer Stack,Device Variation,Device Footprint
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