Acceleration and energy consumption optimization in cascading classifiers for face detection on low-cost ARM big.LITTLE asymmetric architectures
CoRR(2024)
摘要
This paper proposes a mechanism to accelerate and optimize the energy
consumption of a face detection software based on Haar-like cascading
classifiers, taking advantage of the features of low-cost Asymmetric Multicore
Processors (AMPs) with limited power budget. A modelling and task
scheduling/allocation is proposed in order to efficiently make use of the
existing features on big.LITTLE ARM processors, including: (I) source-code
adaptation for parallel computing, which enables code acceleration by applying
the OmpSs programming model, a task-based programming model that handles
data-dependencies between tasks in a transparent fashion; (II) different OmpSs
task allocation policies which take into account the processor asymmetry and
can dynamically set processing resources in a more efficient way based on their
particular features. The proposed mechanism can be efficiently applied to take
advantage of the processing elements existing on low-cost and low-energy
multi-core embedded devices executing object detection algorithms based on
cascading classifiers. Although these classifiers yield the best results for
detection algorithms in the field of computer vision, their high computational
requirements prevent them from being used on these devices under real-time
requirements. Finally, we compare the energy efficiency of a heterogeneous
architecture based on asymmetric multicore processors with a suitable task
scheduling, with that of a homogeneous symmetric architecture.
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