Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimization
CoRR(2024)
摘要
Memory is a critical design consideration in current data-intensive DNN
accelerators, as it profoundly determines energy consumption, bandwidth
requirements, and area costs. As DNN structures become more complex, a larger
on-chip memory capacity is required to reduce data movement overhead, but at
the expense of silicon costs. Some previous works have proposed memory-oriented
optimizations, such as different data reuse and layer fusion schemes. However,
these methods are not general and potent enough to cope with various graph
structures.
In this paper, we explore the intrinsic connection between network structures
and memory features to optimize both hardware and mapping. First, we introduce
a graph-level execution scheme with a corresponding dataflow and memory
management method. This scheme enables the execution of arbitrary graph
patterns with high data reuse and low hardware overhead. Subsequently, we
propose Cocco, a hardware-mapping co-exploration framework leveraging
graph-level features of networks. It aims to minimize communication overhead,
such as energy consumption and bandwidth requirements, with a smaller memory
capacity. We formulate the graph-partition scheduling and memory configuration
search as an optimization problem and employ a genetic-based method to achieve
efficient co-exploration for large and irregular networks. Experiments
demonstrate that Cocco obtains lower external memory access, lower bandwidth
requirements, and more stable optimization for graph partition compared to the
greedy algorithm and dynamic programming introduced in prior works. Cocco also
reduces the costs by 1.89
typical methods.
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