A Serial-Parallel-Based 4-Bit Novel Multiplier: Design, Implementation, and Performance Analysis

Multiplication is a fundamental mathematical operation that holds significant importance in various fields. Efficient multipliers are crucial for power and time-efficient electronic circuits in applications, such as, digital signal processing, cryptography, and image processing. This paper proposes a novel 4-bit multiplier design based on column reduction technique and implemented on the Basys3 Artix-7 FPGA board using the Xilinx Vivado tool. The FPGA implementation results show an increase in performance by 9.27% and a decrease in power consumption by 8.58% compared to existing approaches. Comparative analysis with standard multipliers like Array, Braun and Wallace Tree validates the superiority of our design. The proposed multiplier is successfully synthesized, implemented and functionally verified in UMC 65nm technology using the Synopsys EDA tool, confirming its effectiveness. Overall, our design offers significant advantages in terms of power consumption, time delay, and performance in FPGA and Synopsys results, contributing to the advancement of efficient multipliers in electronic circuits.