On Short Channel Effects in High Voltage JFETs: A Theoretical Analysis

F. Monaghan,A. Martinez, J. Evans, C. Fisher, M. Jennings

Power Electronic Devices and Components（2024）

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摘要

•Modelling of a vertical SiC JFET using TCAD has been completed in this study•Threshold Voltage is affected by lateral implant straggling•DIBL is identified as a premature failure mechanism in vertical JFETs•Both gate junction depth and mesa width are shown to be related to DIBL

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关键词

Silicon Carbide,JFET,Drain Induced Barrier Lowering,Short Channel Effects,Breakdown Voltage,Model

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