Automatic Timing-Driven Top-Level Hardware Design for Digital Signal Processing.

Though hardware auto generators can efficiently generate architectures of different design metrics based on generation formulas, top-level design for digital signal processing remains challenging. In this paper, we propose an automatic timing-driven top-level hardware generation scheme which integrates top-level timing arrangement, code generation and fast evaluation to further alleviate the heavy workload of hardware design for digital systems. To demonstrate the effectiveness of our proposed scheme, a channel impulse response estimator is implemented. It is shown that our scheme can explore design space and optimize hardware architecture automatically with different design constraints.