Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm.

After studying FPGA circuit optimization, this paper improves the simulated annealing algorithm to floorplan the key circuits of the FPGA tile and optimize the wirelength and delay. The paper implements a larger range of interconnect key circuits exchange to explore a larger solution space and obtain better wirelength and delay. The paper also adopts adaptive initial temperature and combines exponential cooling and flexible iterations at different temperatures, allowing the algorithm to fully utilize time for optimization at an appropriate temperature, aiming to achieve better wirelength and delay. Experimental results show 5.14% and 1.27% average optimization in wirelength and delay respectively, compared to the traditional simulated annealing algorithm. Also, the traditional SA algorithm took nearly three times the time to achieve the optimization effect of the new algorithm. In addition, compared to previous works, this paper is able to obtain a reasonable floorplan that minimizes wirelength and delay, providing more accurate wirelength information for load modeling.