A Bang-Bang Phase Detector for PAM-N Signaling.
2023 IEEE 15th International Conference on ASIC (ASICON)(2023)
摘要
Phase detector design for clock and data recovery (CDR) becomes challenging as the number of pulse amplitude modulation (PAM) levels increases. This paper presents a bang-bang phase detector (BBPD) architecture for PAM with N-level signaling (PAM-N) that balances the complexity and performance by utilizing an edge slicer whose threshold is adjusted according to the types of transitions. To accommodate high-speed applications, one-eight-rate architecture with carefully chosen timing is exploited. The validity of the proposed BBPD is examined for its PAM-4 and PAM-6 versions in 28 nm CMOS technology.
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关键词
Bang-Bang,CDR,Multi-mode,NRZ,PAM-6,PAM-4,PAM-N,Phase Detector
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