A COT-based Highly Efficient Hybrid 3-Level Buck Converter for Next-Generation Memory Module Designs

This paper proposes the design of a useful COT-based high-efficiency Hybrid 3-Level Buck Converter for DRAM Memory Modules. The proposed Buck Converter can achieve an efficiency of 82.8%, surpassing the JEDEC efficiency spec of 82%, even when the DCR of the inductor increases from 10m Omega to 120m Omega. Additionally, it allows for a 75% reduction in the external inductor size, reducing it from 1008 to 0805. Consequently, the overall size of the PMIC block in the DDR5 Memory Module, which includes the PMIC, four inductors, and twelve bulk capacitors, can be reduced from 16.5 x 10.0 mm to 10.5 x 7.0 mm. This reduction in size enables an increase of up to 376uF (47uF 8ea) in the capacitance of High-Density Memory Modules, leading to improved power integrity (PI) performance of the entire Memory Module.