RA-Aware Fail Data Collection Architecture for Cost Reduction

As fault occurrence probability has increased with corresponding increases in memory density and capacity, memory test and repair have been widely used. However, the total cost for these has increased dramatically due to the increased cost of automatic test equipment (ATE) and the time required for redundancy analysis (RA). The increase in ATE cost has been caused by the increased size of fail address memory, where memory fault information is stored during memory test. The RA time has also increased because the difficulty encountered during fault analysis has increased in proportion to the increase in the number of memory faults. To address these problems, an RA-aware fail data collection architecture is proposed. This includes a new fail address memory structure that can significantly reduce the fail address memory size. Moreover, the architecture can integrate memory fault information using simple calculations without any data losses. In addition, unnecessary memory fault information can be eliminated easily with efficient data encoding to reduce the data size. Furthermore, since some information required for fault analysis in memory repair can be collected during memory test, the RA time needed to find memory repair solutions is also reduced without any degradation in the repair rate. Consequently, the total cost for memory test and repair can be considerably reduced by reducing the cost of ATE and the RA time. Experimental results reveal that the fail address memory size and RA time can be reduced by an average of 63% and 41%, respectively, with the proposed architecture.