An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory.

Spiking neural networks (SNNs) associated with neuromorphic hardware architectures inspired by the human brain are considered to have promising prospects in ultra-low power applications such as Internet of Things (IoTs) and edge computing devices due to their spike-based information processing and transmission. In this paper, we propose a fully event-driven, clock-free and mixed-signal CMOS design of a highly energy-efficient spiking neural network hardware architecture for visual recognition tasks. The SNN algorithm we employ is based on the Rectified Linear Postsynaptic Potential function (ReL-PSP), which operates in the continuous time domain and dovetails perfectly with our completely clock-free hardware design. In combination with current domain SRAM CIM (Computing-in-Memory), energy expenditure of the I&F (Integrate-and-Fire) neuron and synaptic array has been notably reduced. Simulation results under 28nm CMOS technology indicate that our design achieves 96.92% classification accuracy on MNIST handwritten digit recognition, with only 1.38nJ energy consumption per image and 10us latency.