A Compact Low-Power Time-Domain Winner-Take-All Circuit.

In this paper, a compact low-power time-domain winner-take-all (WTA) circuit is proposed. The proposed WTA circuit has a global inhibition signal to inhibit the inputs except the one exceeding the threshold voltage first. The inhibition signal has another important role in preventing redundant transitions in the circuit, resulting in a substantially reduced switching power consumption. Furthermore, the inhibition signal allows the proposed WTA circuit to be configured as a fully parallel structure even for a large number of inputs, achieving compact area and lowlatency operation. The proposed WTA circuit was designed in a 2Snm CMOS process. The performance evaluation results indicated that the proposed WTA circuit improved energy consumption by 88% and layout area by 73.2% as compared to conventional WTA circuits.