Design of Phase-Interpolator Based Open-Loop Fractional Output Dividers.
2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)(2023)
摘要
The architectural and circuit design aspects for designing an open-loop fractional output divider used in a clock generator are considered. The analysis of two classical schemes for phase interpolation shows that Type II is preferred, as using a replica circuit and a special driver of the phase generators allows obtaining a simulated RMS jitter of 680 fs.
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