An ultra-low quiescent current power-on reset circuit with DDPG method

An ultra -low quiescent current power -on reset (POR) circuit with double -delay pulse generation (DDPG) method is presented in this paper. The circuit is designed for non-volatile memory (NVM) systems, aiming to ensure reliable initialization and enhance overall efficiency. To address the challenge of inaccurate trigger-point voltage caused by process, voltage, temperature (PVT) and ramp time variations, a novel pulse generation method is proposed. Additionally, the circuit further improves the reliability of pulse duration through the utilization of low-cost current reference generators. Implemented in standard 40 nm CMOS technology, the delay -based POR circuit consumes only 0.24 nA quiescent current and occupies a compact area of 25.6 mu m x 102 mu m. The simulation results demonstrate a typical pulse duration time of 28 mu s, with a temperature coefficient (TC) of 101.4 ppm/C-o. The high reliability and low overhead of this circuit make it suitable for NVM systems and other fast power -on applications.