A Hybrid Calibration Technique for Bit-Weight Errors in Pipelined-SAR ADCs

This paper presents a calibration technique for capacitor mismatches and inter-stage gain error in a pipelined-SAR ADC. Foreground calibration scheme is employed for capacitor mismatches that are immune to voltage-temperature (VT) variations while a background calibration method is used to obtain the coefficient of the inter-stage gain. The proposed hybrid calibration technique is independent of the input signal distribution. Moreover, common mode voltage can be avoided by splitting the capacitors in the digital-to-analog-converter (DAC), thereby saving hardware while maintaining the calibration accuracy. The residue voltage swings are the same in both foreground and background calibration modes through the use of a split switching method, and hence the inter-stage amplifier linearity is not degraded. Simulation results show that, based on 14-bit 100MS/s pipelined-SAR ADC structure, the spurious-free dynamic range (SFDR) can reach l08.5dbc and signal to interference plus noise ratio (SNR) can reach 85.7db after using the proposed calibration method.