A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology

Fault tolerance is crucial for mission-critical FPGA-based systems in radiation environments. Soft-core processors in these systems, performing both control and computational tasks, require efficient soft error mitigation techniques to enhance their fault tolerance. In this paper, we investigate the variation trends in the fault tolerance of various processor components as the software workload changes. Based on our investigation, we propose a reconfigurable soft error mitigation framework that dynamically switches the hardening strategies for the processor according to the running workloads. The innovative application of dynamic partial reconfiguration technique in FPGAs enables time-multiplexing of the same circuit region to accommodate various hardening schemes, consequently achieving high area efficiency. We apply the framework to an open-source dual-issue superscalar RISC-V processor on a Xilinx ZCU102 FPGA board. Compared to traditional spatial redundancy-based hardening techniques, the proposed framework achieves a 20.84 % reduction in LUT utilization and a 20.53 % reduction in flip-flop utilization. The effectiveness of our framework has been evaluated through fault injection campaigns. The results indicate that, on average, only 0.05 % of faults would lead to system failure after hardening. Therefore, our work offers a new perspective on dynamic soft error mitigation in reconfigurable systems.