A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy.

The demand for area-efficient, low-power memory circuits is increasing exponentially with the development of wearable devices. Emerging FinFET technology drives STT-MRAM designs to better meet this need. However, comprehensive optimization of STT-MRAM circuits regarding power consumption, area, and sensing yield is still a severe challenge. This work focuses on a low-power, area-saving access strategy without sensing yield loss based on 1T1MTJ for STT-MRAM in FinFET technology. In this paper, FinFET-based MRAM bitcells are constructed, and the advantages of using FinFETs for MRAM design are analyzed. Moreover, a triple-balanced voltage sense amplifier (TB-VSA) for sensing 1T1MTJ is proposed, offering comprehensive optimization in area, power, and sensing yield. Simulation is performed based on 14-nm FinFET logic process. Monte Carlo (MC) simulation shows that the proposed sense amplifier exhibits excellent tolerance to PVT variations, and it achieves at least 47% energy and 35% area saving compared to previous works.