Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre -amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at Vid =1 mV and VCM= 0.7 V with VDD= 1.2 V andfs= 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ.