Robust Pattern Generation for Small Delay Faults Under Process Variations.
2023 IEEE International Test Conference (ITC)(2023)
摘要
Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectiveness of such patterns, different circuit instances may show a different fault coverage for the same test pattern set. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations due to the computational complexity. A statistical learning scheme maximises the coverage of SDFs in circuits following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults (TFs) with fast timing-aware fault simulation on GPUs. Simulation experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detection while the fault coverage even increases.
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