Damage Mechanisms in Through-Silicon Vias Due to Thermal Exposure and Electromigration

Recent development in heterogeneous integration for high-performance chips (HPC) demands higher power, which induces a higher level of current density per through-silicon via (TSV) and redistribution layer (RDL) interconnects. Change in electrical and thermomechanical properties during long-term current stressing can result in negative impact on signal integrity and reliability of the device. In this study, test samples of Si interposers containing TSVs with a multilayered RDL structure at the top were tested under current densities ranging from 1 × 105 A/cm2 to 2.5 × 105 A/cm2 at 200°C in vacuum. Microstructural changes were observed in the current-carrying TSVs, and the circuit resistance increased sharply during the test. This increase was associated with several damage modes, including migration of Sn and Ag from solder, and Ni from under-bump metallization, driven by electromigration, leading to alloying and formation of reaction products. A volume increase associated with phase transformations and electromigration-induced void formation defects are identified under highly accelerated testing conditions, which potentially affect the long-term reliability of TSV-containing structures and need to be considered in design and manufacturing protocols for devices and packages.