Node Ringing Reduction of Synchronous Buck Converter

This paper discusses the issue related to the switching regulators operated at high switching frequencies, where it is necessary to eliminate the influence of parasitic components of the converter's main circuit. In more detail it deals with the node-ringing phenomena, which is typical for synchronous buck converters. The existence of the parasitic inductances arising from the printed circuit board conductive paths, induce voltages, which are several times higher than nominal input voltage, thus it increases the risk of damage of the power transistors. Therefore, optimization of the circuit is required to reduce the voltage spikes and therefore improve safety margin related to nominal operation. In this paper, node-ringing phenomena is introduced, while the optimization methodologies for its reduction are described and verified by experimental analysis.