A new Hardware Efficient Approximate Subtractors for Error Tolerant Applications

Abstract As technology advances, humans will have more opportunities to build designs that are more efficient and are capable of dealing with future challenges. Approximate computing is one such trend in the design of Very Large Scale Integration (VLSI) systems. This strategy is employed in cases where the design’s performance is critical and it is especially useful for energy-efficient designs. There are different subtractors proposed in various papers, these designs are brought together to analyze the strategies and find out the drawbacks of the existing subtractors. This helps in designing a new set of subtractors to overcome these drawbacks. This paper proposes four possible approximate subtractor designs, each with its own set of capabilities. These designs are simulated and the results are then analyzed to assess the circuit’s efficiency. According to the results of the evaluation, the proposed subtractors are substantially more efficient than the exact and the existing subtractors. A new Efficient Approximate Subtractors The first two proposed subtractor designs are utilized as circuits with high energy efficiency, and comes under the hardware efficient circuits. Whereas the remaining designs prioritize in precision and delay factors, out of which a completely accurate subtractor has been proposed. These designs can be utilized for a variety of applications under logical circuits’ arithmetic operations, as well as for numerous error-tolerant applications. Overall, this paper proposes a comprehensive set of subtractors.