SiGe Selective Etching to Enable Bottom and Middle Dielectric Isolations for Advanced Gate-All-Around FET Architecture

Hikaru Kawarazaki, T. Nakano, Takaaki Ishizu, Takayoshi Tanaka, Wen Li, Jason Chen, Tomoko Kawashima, Aibin Wu,Farid Sebaai, Ju Geng Lai, Oniki Yusuke,Efraín Altamirano-Sánchez

Solid State Phenomena(2023)

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摘要
Formulated chemical ACT ® SG6xxx series demonstrated SiGe etching selective to SiGe with lower Ge concentration. SiGe etching rate on SiGe/Si multi-stack shown steep trend as a function of Ge concentration, resulting in 338 of selectivity between SiGe30% and SiGe15%. Also, apparent loss on SiN and SiO 2 was not observed. Moreover, SiGe etch rate was not impacted by chemical flow in the beaker. It suggests reaction-controlled based etching, which leads to good within wafer uniformity in etching rate of 300mm wafer spin processing. In conclusion, ACT ® SG6xxx series is a promising option for the formation of BDI/MDIs in Nanosheet, Forksheet and CFET.
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关键词
middle dielectric isolations,gate-all-around
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