(Invited) Gate Stack Design for Field-Effect Transistors Based on Two-Dimensional Materials

1.Introduction Two-dimensional(2D) materials hold the promise to allow for ultrathin channels built of single atomic monolayers in ultimately scaled field-effect transistors (FETs). Due to this small thickness, an enhanced gate control is achieved while at the same time sizable mobilities in the 2D materials can be maintained[1]. In this way, the on-current density of the devices could potentially be increased to up to 1mA/μm by stacking six nanosheets on top of each other, combining p-type and n-type FETs in vertical integration. Even though FETs based on 2D materials hold a lot of promise, numerous challenges still need to be overcome. One of the most serious obstacles is the identification of a suitable gate stack. Over the last years, several insulators have been suggested, including layered insulators like hBN[2], ionic insulators like CaF 2 [3], amorphous high-k dielectrics like HfO 2 [4], see Fig.1. In addition, crystalline perovskites like SrTiO 3 [5] or native oxides like Bi 2 SeO 5 [6] have been explored. However, which of these materials provides the best performance is at the moment unclear and needs to be evaluated according to the criteria of scalability (Section 2), the minimization of charge traps (Section 3), and batch-processing compatible deposition technology for double-gated device designs (Section 4). 2.Scalable Gate Stacks High-performance FETs require a high on/off current ratio and steep subthreshold slopes. In order to preserve these characteristics in devices with ultimately scaled channel lengths, the insulator capacitance needs to be higher than 1.5μFcm -2 , corresponding to a capacitive equivalent thickness smaller than 1nm. At the same time, if the insulator thickness becomes too small, the gate leakage current often easily exceeds the low-power limit of 0.015 Acm -2 , thereby increasing the standby power consumption in the off-state. In fact, the gate leakage currents through thin hBN layers are high, rendering it unsuitable as a gate insulator for scaled FETs, while CaF 2 , HfO 2 or Bi 2 SeO 5 show promise[7]. 3.Minimizing Charge Traps The gate insulator should form a van der Waals interface with the 2D semiconductor, as otherwise, interface traps will degrade the carrier mobility and the sub-threshold slope[8]. Charge traps within the insulators cause limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in Bias Temperature Instabilities. As a consequence, the stability can be enhanced if the defect bands in the gate insulator are energetically far away from the conduction and valence band edges[9]. Thus, the number of electrically active charge traps can be minimized by selecting a suitable combination of 2D semiconductor to insulator or by reducing the width of the defect bands by using crystalline insulators. 4.Deposition Technology Gate insulators need to be deposited on top of 2D semiconductors for top gate formation. However, the inert planes of 2D materials inhibit direct nucleation of insulators from the gaseous phase in an atomic layer deposition process. In this context, a promising approach is to use a self-assembled polymer monolayer to nucleate the precursors[4]. Molecular beam epitaxy is an alternative growth approach for gate insulators which offers the advantage of van der Waals epitaxy for layered materials, where the lattice-matching conditions are relaxed[10]. In order to avoid the growth of the insulator on top of the 2D semiconductor altogether the in-situ oxidation of the 2D semiconductor to its native oxide is a promising option, like for Bi 2 SeO 5 . 5.Conclusions Even though many novel insulator systems for 2D FETs have been proposed over the last couple of years, it is still unclear which of them best meets the requirements formulated. The most important questions to be addressed in the future will be to identify systems with reproducibly small interface and border trap densities and high thermal stability and to develop suitable batch-processing compatible top gate deposition methods for these material systems. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no.101055379. References [1] S.Das et al., Nature Electronics 4, 786(2021). [2] T.Roy et al., ACS Nano 8, 6259(2014). [3] Y.Y.Illarionov et al., Nature Electronics 2, 8(2019). [4] W.Li et al., Nature Electronics 2, 563(2019). [5] A.J. Yang et al., Nature Electronics 5, 233(2022). [6] T.Li et al., Nature Electronics 3, 473(2020). [7] T.Knobloch et al., Nature Electronics 4, 98(2021). [8] T.Knobloch et al., Nanomaterials 12, 1(2022). [9] T.Knobloch et al., Nature Electronics 5, 356(2022). [10] L.A.Walsh et al., Applied Materials Today 9, 504 (2017). Figure 1: Schematic of a top-gated, scaled FET with an MoS 2 channel and a HfO 2 gate oxide. Figure 1