A Comprehensive Simulation Framework to Validate Progressive Read-Monitored Write Schemes for ReRAM

This work introduces a simulation framework for behavioral models of resistive switching devices. Along with variability, the presented approach incorporates dynamic bias-dependent switching behavior, transition faults (soft errors) attributed to the fading memory property, as well as stuck-at faults (hard errors) due to overstressing of RS devices. All these attributes are developed as model add-ons in a compact and SPICE-compatible form for comprehensive circuit simulations towards the validation of read-monitored progressive WRITE schemes for practical resistive memory (ReRAM) applications.