GBW Optimization in Two-Stage OTAs Operating in Weak Inversion

An experimental study on the optimization of two-stage OTAs using different output stages and compensation techniques is presented. Optimization tries to maximize GBW for a given quiescent current consumption, and to this aim transistors are operating in weak inversion. A test chip prototype including 8 different two-stage OTA configurations has been fabricated in a standard 0.5-mu m CMOS technology. Measurement results validate the benefits of the optimization technique employed in different design scenarios.