Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks

ADVANCED INTELLIGENT SYSTEMS(2024)

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摘要
Herein, dual-gate field-effect transistors (DG FETs) fabricated on Si substrate and a corresponding NOR-type array designed for low-power on-chip trainable hardware neural networks (HNNs) are presented. The fabricated DG FET exhibits notable endurance characteristics, with the subthreshold swing remaining consistently within a 2.45% range of change and Delta Vth per cycle maintaining stability at 4.5% over repetitive program and erase operations, up to 104 cycles. Furthermore, a multilevel characteristic is achieved through low-power program/erase operations based on Fowler-Nordheim (FN) tunneling, which exhibit 0.09 and 0.99 fJ per spike, respectively. These characteristics provide the HNN stability, along with high performance and power efficiency. The NOR-type array in this work demonstrates selective update and bidirectional vector-by-matrix multiplication capabilities. This enables on-chip training based on a gradient descent algorithm, without the need for an additional array for backpropagation. Subsequently, a simulation of the Modified National Institute of Standards and Technology classification is conducted to evaluate the accuracy and training power consumption of the proposed device in comparison to other two-terminal memristor devices. The results show that the DG FET array achieves superior accuracy while maintaining over 180.4 times higher energy efficiency, demonstrating the potential of the DG FET as a promising candidate for low-power HNN applications. Herein, dual-gate field-effect transistors (DG FETs) for low-power on-chip hardware neural networks (HNNs) are reported. The saturation characteristic of the device provides robustness against voltage fluctuations. The NOR-type DG FET array is capable of both bidirectional operation and selective updates based on Fowler-Nordheim tunneling, reducing the latency and power consumption during the training phase of the on-chip trainable HNNs.image (c) 2023 WILEY-VCH GmbH
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关键词
dual-gate field-effect transistors,gradient descent algorithms,hardware-based neural networks,NOR-type arrays,on-chip training
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